I have just had a design rejected by JLCPCB because a hole in a pad would have cut a trace in the bottom layer.  The way EasyEDA displayed the pad, it wasn't clear to me that there were holes.  I have rerouted the tracks now, but here is an image of the top and bottom layers with holes indicated in the top, but not in the bottom. As you can see, those holes don't appear on the bottom layer though their description is 32mil diameter plated holes (sorry, description in above image was of the pad, not the hole).  So these are thermal vias.  They should appear in the bottom layer shouldn't they? Now I am concerned that there will still be problems for the fabricators because of these inconsistencies.  Does something need to be done about this pad definition?  FWIW, the pad in question was the default VQFN24 associated with the TI MSP430FR2433 microcontroller. Thanks for any advice.