Thermal relief under IC's; different size vias
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PeterL 2 weeks ago
I have a 4 layer board and I wish to create a design rule that allows 2 different size of vias on the same GND net without causing an error.  How can this be done? Specifically, in my case, normal network GND vias are .6/.3 (dia/hole mm) and I want some smaller GND vias to sit under IC's for thermal relief.  When I create them the design rule checker throws an error because it wants them to be .6/.3.  The smaller vias would still be within JLCPCB manufacturing guidelines. I think the issue come down to understanding how 2 sizes of vias can co-exist on the same network?
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andyfierman 2 weeks ago
Can you not change the Design Rules to suit the smaller sized vias and then the larger ones will not create an error?
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PeterL 2 weeks ago
@andyfierman Just tried and .. ahHa .. it works a charm.  Thanks for the fresh thought on it; It requires a little care when adding new vias later but works well.
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andyfierman 2 weeks ago
This post might help regarding adding thermal relief vias: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)
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PeterL 2 weeks ago
@andyfierman Thanks .. It was helpful.  I carefully read it line buy line.
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