I have a 4 layer board and I wish to create a design rule that allows 2 different size of vias on the same GND net without causing an error.  How can this be done? Specifically, in my case, normal network GND vias are .6/.3 (dia/hole mm) and I want some smaller GND vias to sit under IC's for thermal relief.  When I create them the design rule checker throws an error because it wants them to be .6/.3.  The smaller vias would still be within JLCPCB manufacturing guidelines. I think the issue come down to understanding how 2 sizes of vias can co-exist on the same network?