1) I have not tried this but you may find that rebuilding your footprint so that it is on the top layer may resolve the track layer display error. Then if you want the footprint on the bottom layer, place it on the top layer then manually swap it onto the bottom layer. 2) The following does not address your question above but it does point out the issues that you will have with your footprint: When placed in a PCB, the footprint itself will generate DRC errors at each element of the footprint so each pad and each end of the tracks that you have used in the creation of the footprint will flag up a DRC error. There is currently no way to avoid these DRC errors because at present EasyEDA does not have an element that functions as a "net splitter" or a "net tie". For more on this please see: [https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60](https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60)

@andyfierman I tried your first suggestion and recreated the component on TopLayer side. After integrating it into the circuit and moving it to the BottomLayer, the pads are also on the BottomLayer. The connections between them are also blue, but are graphically displayed again above the red connections on the TopLayer. Is there anything else I could try? Assuming there is a solution to my problem, would the DRC errors be a problem for production (SMT)? Or can they be ignored? regards

What you are seeing is a display problem (bug). When you check the Gerbers (which having gone through the essential checklists in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a), you will of course do), you should find that the copper is in fact in the right places. As for the DRC errors, they do not affect the manufacturability of the PCB. They just add to the list of things that you must check to identify what are "real" DRC errors that may result in trash boards if you ignore them as opposed to those that are a result of using cuttable links as a solution in EasyEDA, and which you can ignore.