Trace width for 10 Amps
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droodlol 1 week ago
Hello, I would need to design a board to transport 10Amps (MAX) at mains voltage 230V. I have initially defined 2mm width traces on one side for this. I have checked this with calculators such as: [http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/](http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/) First of all what is the default THICKNESS of a standard PCB line? (since it seems this cannot be set in EasyEDA although I can do double sided traces to double up on this with VIAs) Is this calculator any valid for your site?
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andyfierman 1 week ago
You'll find the default copper thickness for boards made by jlcpcb on the PCB order page (in terms of ounces) and here: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) Note that if you wish to increase the current capacity of a track by soldering wires over it then you can remove the solder mask over selected tracks using the "Expose Copper" button. Don't forget that the clearance around tracks vs. the voltage they are at is just as important as the copper width and thickness for the current they carry and the acceptable temperature rise at that current.
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droodlol 1 week ago
Hello, I'm sorry but that datasheet is not clear to me: | | | | --- | --- | | Finished Outer Layer Copper  | 1 oz/2 oz | Now which one? 1 oz or 2 oz. As I said I would order 2 sided PCB no extras and I don't want to expose the copper for safety reasons since this is high voltage. Even if I count it with 2 the calculator says that the required trace width is: 9.36 mm which is almost 1 CM! Way too thick. Correct me if I'm wrong but is this calculation correct and I would really need almost 1cm width?!
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andyfierman 1 week ago
When you place your order for your pcb you can select the copper weight as 1 oz copper (~35µm thick or 1.4 mils) or 2 oz copper (70µm thick or 2.8 mils). The trace width calculator you have used is correct. The trace width will depend on the copper weight, a higher copper weight results in a narrower trace width. In all cases the calculation also depends on what temperature rise you can accept in the current carrying conductor. The conductor has a resistance R ( which also increases with temperature) therefore it dissipates power due to I^2R where I is the current in the wire. Therefore you need to decide what temperature rise you can accept above the PCB maximum operating temperature, bearing in mind that other components on the board may also be contributing to the overlap PCB temperature rise above ambient.
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MikeDB 3 days ago
For that kind of voltage and current, you use as wide as you can manage, but with spacings of 25 or even 50 mil.  I generally aim for about 1cm wide.
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cjohnson 1 day ago
Take a look at this pdf: [http://electronica.ugr.es/~amroldan/cursos/2014/pcb/modulos/temas/IPC2152.pdf](http://electronica.ugr.es/~amroldan/cursos/2014/pcb/modulos/temas/IPC2152.pdf) Look at page 6, it depends what you're designing for in terms of *C rise over ambient temperature.
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droodlol 12 hours ago
Hi, Just one more question: I can't increase the width anymore but I can doubleside the board, making one fat trace on both sides. Is it actually makes it better if I connect these traces on multiple points with VIAs or not?
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andyfierman 10 hours ago
Depends on the components you use on your PCB. If you have a through-hole connector going to a through-hole relay then the pins may provide a better connection between the layers than using vias. The problem with vias on their own is that they reduce the effective track width and they have only very thin copper through-plating so they can end up increasing the resistance and the local temperature rise. If the vias are not capped and are solder filled then that is more likely to be worth doing. If the board is just a one-off then using multi-layer pads with larger holes than vias, which you then hand solder fill is probably a reasonable solution. Maybe @MikeDB knows of some formulae or calculators but similarly to the question of designing arrays of vias to reduce thermal resistance, designing arrays of vias to reduce electrical resistance does not seem to be readily documented on the web in the same way that trace design for current capacity and temperature rise or for voltage clearance or for controlled impedance is.
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MikeDB 4 hours ago
@andyfierman Unfortunately this is one key tool I miss from losing access to professional PCB tools.  Mentor was always best as their tool would allow you to enter the current passing through each track and it produced a full heat-map.  Zuken was a little more primitive but still very useful.   Maybe we will get these tools in EasyEDA one day but I doubt it's even on the radar yet :-)
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