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Track Width and Clearance Warning for unknown reason
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Caster 3 years ago
What's wrong with my PCB design? Tracks are 0.25 mm. Design Rule [mm]: Track Width: 0.25 Clearance: 0.1 Copper Area: Clearance: 0.061 (CPWG) ![Track Width.jpg](//image.easyeda.com/pullimage/5sUM6ZqqMEcHs1lVAFAhcBd8Qz3xhrzmtfbwUnRM.jpeg) ![Clearance.jpg](//image.easyeda.com/pullimage/huDv53cfgvMODXsJsepz77vIO0lgg82fK22phOFw.jpeg)
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andyfierman 3 years ago
@Caster, Please remember to post the url to your public project when asking for help on it: [https://easyeda.com/Caster/gps-lna](https://easyeda.com/Caster/gps-lna) Part of the problem is caused by the way you have constructed pads 1 to 4 in the DQN0004A footprint for U1 using a combination of pads, tracks and Solid Regions: ![image.png](//image.easyeda.com/pullimage/uyBpBQXpYyGNgRaAEWLJh0VIK6LDbuluDQQd2RuB.png) Using anything other than pads in the construction of footprints will generate DRC errors: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)
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Caster 3 years ago
Thank you for your help. I will fixed the pad by using polygon only.
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andyfierman 3 years ago
@Caster, If you rebuild the pads as polygons only then I think all your DRC errors will clear.
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