Got it. The problem is with the formatting of the .subckt what you have pasted in is: \.SUBCKT Si2301CDS D G S M1  3  GX S S PMOS W=500000u L=0\.250u  M2  S  GX S D NMOS W=500000u L=0\.416u RG  G  GX     6 R1  D  3      RTEMP 3E\-2 CGS G  S      100E\-12 DBD D  S      DBD \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*  \.MODEL  PMOS         PMOS \(LEVEL  = 3        TOX    = 1\.7E\-8 \+ RS     = 4\.5E\-2          RD     = 0        NSUB   = 1E16    \+ KP     = 1E\-5            UO     = 400              \+ VMAX   = 0               XJ     = 5E\-7     KAPPA  = 1E\-3 \+ ETA    = 1E\-4            TPG    = \-1   \+ IS     = 0               LD     = 0                  \+ CGSO   = 0               CGDO   = 0        CGBO   = 0  \+ NFS    = 0\.8E12          DELTA  = 0\.1\) \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*  \.MODEL  NMOS         NMOS \(LEVEL  = 3        TOX    = 1\.7E\-8 \+NSUB    = 9E16            IS     = 0        TPG    = \-1\)    \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*  \.MODEL DBD D \(CJO=80E\-12 VJ=0\.38 M=0\.39 \+FC=0\.5 TT=1\.8e\-08 T\_MEASURED=25 BV=20\.5 \+RS=3\.308e\-02 N=2\.756 IS=6\.178e\-05 IKF=1000 \+EG=8\.569e\-01 XTI=2\.641 TRS1=1\.602e\-07\) \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*  \.MODEL RTEMP RES \(TC1=7E\-3 TC2=5\.5E\-6\) \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*  \.ENDS all in one line whereas it should be: ``` ``` ``` ******************************** * Copyright:                   * * Vishay Intertechnology, Inc. * ******************************** *Aug 18, 2014 *ECN S14-1662, Rev. B *File Name: Si2301CDS_PS.txt and Si2301CDS_PS.lib *This document is intended as a SPICE modeling guideline and does not *constitute a commercial product data sheet.  Designers should refer to the *appropriate data sheet of the same number for guaranteed specification *limits. .SUBCKT Si2301CDS D G S M1  3  GX S S PMOS W=500000u L=0.250u M2  S  GX S D NMOS W=500000u L=0.416u RG  G  GX     6 R1  D  3      RTEMP 3E-2 CGS G  S      100E-12 DBD D  S      DBD ************************************************************ .MODEL  PMOS         PMOS (LEVEL  = 3        TOX    = 1.7E-8 + RS     = 4.5E-2          RD     = 0        NSUB   = 1E16 + KP     = 1E-5            UO     = 400 + VMAX   = 0               XJ     = 5E-7     KAPPA  = 1E-3 + ETA    = 1E-4            TPG    = -1 + IS     = 0               LD     = 0 + CGSO   = 0               CGDO   = 0        CGBO   = 0 + NFS    = 0.8E12          DELTA  = 0.1) ************************************************************* .MODEL  NMOS         NMOS (LEVEL  = 3        TOX    = 1.7E-8 +NSUB    = 9E16            IS     = 0        TPG    = -1) ************************************************************* .MODEL DBD D (CJO=80E-12 VJ=0.38 M=0.39 +FC=0.5 TT=1.8e-08 T_MEASURED=25 BV=20.5 +RS=3.308e-02 N=2.756 IS=6.178e-05 IKF=1000 +EG=8.569e-01 XTI=2.641 TRS1=1.602e-07) ************************************************************* .MODEL RTEMP RES (TC1=7E-3 TC2=5.5E-6) ************************************************************* .ENDS ``` However, this subckt is in Pspice syntax so if it still does not work in EasyEDA, try editing the: ``` .MODEL RTEMP RES (TC1=7E-3 TC2=5.5E-6) ``` line to ``` .MODEL RTEMP R (TC1=7E-3 TC2=5.5E-6) ; edited for Ngspice compatibility ``` Or just edit it anyway. :)

@andyfierman Thanks!, Indeed I discovered by double-clicking on the text element, the formatting from the pasted text is preserved. However now I'm getting the dreaded > Error(parse.c--checkvalid): volprobe: no such vector. First I applied the edit you suggested\, and got the above error\.  I then noticed the first SPICE file in the zip \(Si2301CDS\_HS\_PS Rev B\.TXT\) declared > .MODEL RTEMP R (TC1=7E-3 TC2=5.5E-6) So, wondering if that file was better suited for ngSpice I replaced it - but I still get the same error as above. At least now I am getting some feedback in the report, thanks for your help!

Si2301CDS\_HS\_PS Rev B\.TXT is an Hspice format file and I'm not that familiar with their syntax differences to be sure of it will work\. However, I missed a more important point. Unfortunately, most of the schematic symbols in EasyEDA are not suitable for use in simulations and the symbol you have chosen is one of them. For this particular device, I have now made a spice symbol:  and put a copy of the edited model into the EasyEDA library so if you delete the symbol you are using and replece it with the new one, IJW (It Just Works).  :)

You also no longer need to paste the model into the schematic. :)

@andyfierman WOW, thank you so much! It works perfectly!  Thank you!

@andyfierman at the risk of taking it too far, is it possible for you to share the ngSPICE of the circuit? I am curious about the differences - or is there a way to view the SPICE content that I am unware?  Thanks again either way!

Two ways: 1)  2) Run the simulation (sucessfully) then: 

@andyfierman excellent, thank you - I should've been found that myself.  Thanks again for your efforts!

@franklin.simmons, Looking at what you've done so far you have probably already see it but just in case you haven't, this should help: [https://docs.easyeda.com/en/Simulation/Headings/index.html](https://docs.easyeda.com/en/Simulation/Headings/index.html)

@andyfierman indeed I am becoming acquainted with that information.  Given what I've learned since opening this post - from you and the docs - I've successfully created a SPICE component for the Si2302CDS-T1-E3 (n-channel mosfet) which is in a sense the counterpart to the SI2301CDS-T1-GE.  Can't thank you enough for your guidance!

@franklin.simmons. If you're creating parts then this might be helpful too: [How to create findable Footprints and searchable Symbols.](https://docs.google.com/document/d/1ZRkPPMID68mBz9j9RMIJARNSXK12PDULZXP7kiThvDg/edit?usp=sharing)

@andyfierman thanks again, I used that guide to create a SPICE symbol for the FDV304P.  Also, I created another SPICE symbol for the SI2301 with a patched .subckt that works with NGSPICE (the .subckt from Vishay appears to be PSPICE). Unfortunately, the simulations for all 3 aren't producing the expected results using the project  [https://easyeda.com/editor#id=0a3c7fa5ab2a41feb38417d59526aa9e](https://easyeda.com/editor#id=0a3c7fa5ab2a41feb38417d59526aa9e) As it is, I would think  the voltage probe on drain would report essentially zero voltage since gate = source, but all the symbols I've tried report drain = source (= volprobe).  Clearly I have a lot to learn and study. Thanks again for your aid.

Have another careful read through: [https://docs.easyeda.com/en/Simulation/Chapter4-Introduction-to-using-a-simulator/index.html](https://docs.easyeda.com/en/Simulation/Chapter4-Introduction-to-using-a-simulator/index.html) especially the paragraphs on: * A common cause of confusion in simulation is the apparently unexpected behaviour of circuits using open circuit switches.

@andyfierman or in layman's terms, _RTFM_.  Thank you for your guidance!

Well, kind of but in a user friendly sort of way. It doesn't matter how you try to simplify it, doing simulation successfully is not easy in any EDA tool. So it's better if you can read and understand stuff like this for yourself rather than have it sort of scattergunned at you as a series of fragmented Q&A forum posts. I wrote the Simulation eBook Tutorial (and most of the other EasyEDA documentation about simulation) because if I tried to answer all the questions we get about simulation individually, I'd never get anything else done. It was also to try to pass on some of the skills, tips and wisdom acquired over many years in the simulation business. That said, if you know anyone who _really_ understands how to calculate and model the leakage inductances and associated coupling factor of a leaky but otherwise ideal transformer with two separate but identical secondaries, could you let me know? **_:)_**

@andyfierman indeed!  Having finally crawled to [Chapter 7 Configuring Voltage and Current Sources](https://docs.easyeda.com/en/Simulation/Chapter7-Configuring-Voltage-and-Current-Sources/index.html) , the magic began - having been utterly ignorant of spice voltage sources, this was my breakthrough chapter.  I've updated my [public project](https://easyeda.com/editor#id=|0a3c7fa5ab2a41feb38417d59526aa9e|45ea0d9fa2804512afffb0b7942131c1) - perhaps it may be helpful to others with the very steep learning curve of getting such a simulation working.  Not having any formal EE schooling, this was a daunting task. _Awesome support._ Thanks again!