Can you post links to public examples please? Thanks.

https://easyeda.com/thomasx/PLL_Lesson_190805-Mc64DLFX Circuit: untitled Error: unknown subckt: xu1 volprobe1 volprobe2 xu1_3 xu1_4 vdd 0 xu1_7 xu1_8 dlatch Hello , thanks for the fast reply. Above the link to my test circuit.

Sorry Thomas but I can't open https://easyeda.com/thomasx/PLL_Lesson_190805-Mc64DLFX However, I have looked at your schematic: https://easyeda.com/editor#id=LjXi6wuit which does not run for two reasons. 1) The supply labels are wrong for the logic devices to recognise and so connect them to the hidden the VDD pins on U1, U2 and U3. For more about this please see: https://easyeda.com/example/Easy_logic_device_simulation_in_V2_3_x_onwards-RaKIG2oJ5 2) For some reason that I cannot understand, although your schematic looks OK, the spice netlist is corrupted. I have forwarded a modified copy (to correct the supply connections) of your circuit to support to try to see how this has happened. * Note also that you have two netflags called LABEL1 but one one you have a voltage probes volprobe1 and on the other volprobe2 which overwrite the the netflag names. For more about this please see: https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.2jxsxqh and https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.z337ya * Do you still have an issue with the HEF4060BEE?

Oh yes: don't use the HEF4060EE_TEMP. Use the HEF4060EE from the EasyEDA Libs. :)

Hi Thomasx, We have found the problem. It's not a corrupted netlist or a bug. It is a subtle problem that we have not explained very well in the EasyEDA documentation! Many of the EasyEDA logic devices have hidden power pins. If you click on U1, U2 and U3, and press the `I` key and then untick the `Hidden pin` box to make the power pins visible in the schematic you will see that you have accidentally wired across the ends of the pins but that the wires do not have join dots to the nets. If you hide the power pins again and then stretch the VDD wires out by one grid square from the pins on the symbols then the wires will not cross the ends of the pins and they will simply connect via the VDD netlabels. :)

https://easyeda.com/thomasx/PLL_Lesson_190805-Mc64DLFX Hello , thanks for the fast Reply. A

@andyfierman Hello Andy, many thanks for your Patience and your Kind help. Your clear instructions helps a lot. Great Job!!! See you soon sometimes again in this community. thomasx

I hope we have got you running again? :)

https://easyeda.com/thomasx/PLL_Lesson_190805-Mc64DLFX Hello , thanks for the fast Reply. A@andyfierman Hello Andy, all circuits works good!! It's a great pleasure for me to work with EasyEDA. I'm an (very old) electrical ingineer and after a Long serious illness now I could be trained my Memory playfull! It is not my Intention to irritate you with my stupid questions!! Kind regards thomasx

Hi thomasx, `It is not my Intention to irritate you with my stupid questions!!` Not at all! I am always happy to help people out and am even more so if I can help move their projects forward. I have been surprised at the number of older and rebooted engineers there are trying out our amazing tools. We can't always get EasyEDA to do what everyone wants but never be afraid to ask whatever you want to know. :)