min space is 3.5mil [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities)

Thanks, so the DRC in EasyEDA is wrong? I'm working with a 2 layer PCB.

@hdgc, * Your project is private so only you can see it. * What is the part number you are asking about? * "so the DRC in EasyEDA is wrong?" Not really. The DRC clearances are set to defaults. There is no reason why you cannot adjust them and in some cases define classes of nets  so you can have different clearances on different classes of nets. @cnmuggle, The minimum track to track spacing for a single or 2 layer board is 5 mil (0.005 inch): [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) but this question is about unplated hole to track spacing but JLCPCB have not yet updated their page to include this information.

I found this resource: [https://github.com/ayberkozgur/jlcpcb-design-rules-stackups](https://github.com/ayberkozgur/jlcpcb-design-rules-stackups) > 2 layer > > > * 1 oz copper > > * 5mil trace with & clearance > * 0.3mm min. hole diameter > * 0.6mm min. via diameter > * 0.25mm hole clearance so by setting the DRC trace width to 5mm, I get no errors. we'll see what happens! Thanks @andyfierman & @cnmuggle

BTW the USB-C part is C319148.

@hdgc, Be careful with using design rules from anywhere except their published rules at: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) You could find yourself using unsupported values.