Hey, I have also noticed that. To me that seems to be because you'd want just 1 copper area per layer, i.e. GND layer. But what I use is the Solid Region tool which seems to do the job:  Hope that solves your problem!

@deskpro256 Yes you are right. Solid region will do the job but previously I was able to do multiple copper areas (GND + Power rails) per layer. Maybe the updated version of the software doesn't allow it anymore. BTW thanks for your help :)

I don't understand this issue. I cannot reproduce this behaviour. Can either of you post a link to a public example demonstrating of this behaviour?

Hi Andy. I added the test copper area in my USBTiny project PCB: [https://easyeda.com/deskpro256/usbtiny](https://easyeda.com/deskpro256/usbtiny) As you can see in the image, I already have GND copper areas on both the top and bottom layers. But if I try to put another copper area(the dotted line shape) on the top layer with let's say the +5V net, it exists there, but isn't a separate island. If I do it with the solid region tool, it creates the desired result and you can see it added a ratline to +5V on the capacitor pin. 

Sorry: I misunderstood the issue. I think it's this bug: [https://easyeda.com/forum/topic/Create-copper-area-inside-another-inner-first-is-OK-but-outer-first-fails-with-no-warnings-0506e39c469f4873ad08aa65e0e71582](https://easyeda.com/forum/topic/Create-copper-area-inside-another-inner-first-is-OK-but-outer-first-fails-with-no-warnings-0506e39c469f4873ad08aa65e0e71582)

Hi You need to set the copper area order at copper manager. the upper copper has high priority。 [https://docs.easyeda.com/en/PCB/Copper-Pour/index.html#Copper-Area-Manager](https://docs.easyeda.com/en/PCB/Copper-Pour/index.html#Copper-Area-Manager)

Sorry: I forgot about that (again!).