Can anybody explain me why EasyEDA produce the message
“doAnalyses: iteration limit reached tran simulation(s) aborted
Error(parse.c--checkvalid): volprobe1: no such vector.
ngspice-26 done”
when I try simulate this scheme (see below)?
![scheme with capacitor][1]
BUT, if I remove the capacitor “C3 100n” ![scheme without capacitor][2] I get this WaveForm ![output signal][3]
Thanks a lot to all for answers!
[1]: /editor/20171102/59fa3f08a3c84.png
[2]: /editor/20171102/59fa3f50b8ab7.png
[3]: /editor/20171102/59fa3f6e7d26e.png