@kiwi_ed, Your project is private so only you can see it. Please make it public and post the url of the whole project (not just the schematic and/or PCB) back here.

@andyfierman Thanks for the response, but I ended up rebuilding it again. This is the last time this board is going to go in production as a new model has been developed, so a few hours lost wasn't that bad in the end. A bit more on the issue, all components came up as needing updating but only one on the schematic was actually tweaked. Aslo all the DRC errors it produced ( 70-odd ) were components that has "slipped" sideways or just rotated in position. I hope it doesn't do these tricks on the new designs... In all I do like the development environment. Thanks again.

Not really understand your problem. Any images?

@UserSupport If it does it again, I'll attach images. Otherwise we can close this bug report. Thanks.

@UserSupport I can almost guarantee the issue is the net calculations that are done differently between versions of software. Let's say for instance you have a +5V net connected to pin 1 of a resistor, side 2 of the resistor is connected to anode of led, cathode connected to ground. A version last week will call the net between pin 2 of the resistor and the anode of the led R1_1. Next update, we import changes and it will try to change the name of that same net to LED1_1 or something like that. This is actually a pretty big problem on larger projects.

@cjohnson Is this old project created by older version before v4.10?  since v4.10, EasyEDA support multiple netlabels on one wire, we change the net name generation rule.  That will cause this issue. In the future, we will use a new logic to keep the schematic net names same as the PCB net all the time, no matter how you import change.  That is a big change, we need some time for investigation. Thanks

@UserSupport, Hmmm. "...we will use a new logic to keep the schematic net names same as the PCB net all the time, no matter how you import change." This statement seems to say that, after first converting a Schematic to a PCB, it is then the PCB that becomes the document that controls net naming. In EasyEDA, the Schematic has always been the master document because changes to it are updated/imported into the PCB. This is referred to as "forward annotation". At the moment there is no "back annotation" mechanism for changes made in the PCB to be passed back into the Schematic. Suppose the user makes a change to a net name or adds a component which splits a net into two or more nets, how will those changes to net names in the schematic be handled to pass them into the PCB? Could you not just look at the version of EasyEDA used to create the Schematic and PCB and just use a different set of rules depending on the EasyEDA version number?

@andyfierman Yes, forward and backward annotation will be supported in the future.