I have two versions of a footprint, version 1 using two pairs of Top and Bottom layer pads via'd together and version 2 using Multilayer pads with a single Auto-placed via joining top and bottom layers. Both now have the central 13mm hole in place.
![image.png](https://image.easyeda.com/pullimage/lePRfbXOb5Hr8es876x8iGNON2KuIUSb0y7VukiY.png)
The footprint should have a central cutout as in the drawing below:
![T10 footprint in color measurements.jpg](https://image.easyeda.com/pullimage/OTKrBiz7oXGWXaAC32OTy1H3891tSUvT3XCakoih.jpeg)
In both versions, the central cutout shape is created by placing a 13mm diameter Hole and also placing a Solid Region with radiused ends on the same 0, 0 centre.
The JLCPCB Gerber viewer shows that in both of them, the central cutout shape is correctly formed:
![image.png](https://image.easyeda.com/pullimage/CXEUPBDZ3hH9MejBObaegSmYMIvhCQ7iVOBo2vs8.png)
There's a Schematic Symbol with the version 2 footprint assigned to the Package attribute and a simple schematic and PCB that demonstrates it together with the same symbol but with the Package attribute edited to assign the version 1 footprint to it:
![image.png](https://image.easyeda.com/pullimage/3VSyaeawY1d3zN1R4C89Yu23oWQIFym795TaiW7H.png)
![image.png](https://image.easyeda.com/pullimage/Lwd33y0J6I8vnYy21c0XS4DmiIkHgVbNQu6TwCwA.png)
The schematic converts to PCB OK but there are lots of DRC errors in both footprints caused by the Solid Region set to No Solid. You can safely ignore them but I believe that using the Solid Region Tool in this way in a PCB Footprint should just not create these DRC errors.
![image.png](https://image.easyeda.com/pullimage/esbdLHlbtXLIefmPvrfj8M9elPdqsVEw33gzmWDI.png)
I was going to try use the Arc Tools to create the required round ended slot directly in the Board Outline layer to replace the Solid Region to see if that avoided the DRC errors but after updating to V6.3.39, I can no longer easily create such a shape.
In fact I originally used the Arc Tools to create the shape that is now created by the Solid Region but didn't check it to see if there were any DRC errors. Then I had the "better" idea of using the Solid Region tool but that was yesterday using V6.3.22. Now having auto-updated to V6.3.39, I no longer have the option of going back to trying the direct Board Outline approach.
I have raised a separate Bug Report about the loss of functionality of the Arc Tools.
Chrome
80.0.3987.87
Ubuntu
EasyEDA
6.3.39