Hi folks !
How does one allocate the VCC and GND pins to be automatically tracked at layout time, please ?
Thanks
John
Hi folks !
How does one allocate the VCC and GND pins to be automatically tracked at layout time, please ?
Thanks
John
Sorry for the vague question !
Your item No 2 is what I'm trying to do.
It's how does one assign VCC and GND to be routed at PCB conversion time - without tying either power pin to a power supply in the schematic.
Add the VCC and GND pins to the Schematic Symbol as normal when constructing a symbol for an IC.
If there are other supply pins, add them and ensure they have unique names such as VCC2, VEE, VDD, VSS and so on.
In the schematic add netflags for supplies of the same names as those on the symbol.
Place the symbol.
If you do not want the supply pins on the symbol to be visible in the schematic select the symbol then press the "I" key and then hide the supply pins in the dialogue box that opens.
This works fine for things like logic gates or opamps where there may be several devices run off the same rails but can get very messy for things like processor chips and FPGAs where there may be several different rails. It is also very unhelpful when it comes to giving any clues as to which supply decoupling capacitors are associated with which pins on which chips.
The section "Creating symbols for multi-part devices using Sub Parts." in (2.3) in (2) in:
https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a
describes a much better way to create symbols not just for things like dual or quad opamps and logic gates but also for complex multipart devices such as processors and gate arrays by splitting them into multi-part symbols using Sub-Parts. By splitting say a quad opamp into 5 symbols one of which is jus for the power supply pins, you get a nice symbol to connect the supplies and the associated decoupling cap(s) and which can then be put in a corner or on a separate sheet avoid clutter in the schematic but still preserve the information about essential supply connections and device decoupling in a way that makes it obvious durint payout which cap belongs to which device and so minimises mistakes of misplacement and omission.
For big digital devices this is also a nice way to split them up into manageable blocks for things like the analogue I/O, serial interfaces, parallel I/O etc., instead of having one big symbol that everything has to be routed.
@JohnAlfred,
Sorry but I don't understand your question and its context.
Are you asking about: