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Via connectivity is seriously broken in 4 (and maybe more than 4) layer boards with planes.
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andyfierman 2 years ago
@UserSupport, **Via connectivity is seriously broken in 4 (and maybe more than 4) layer boards with planes.** **Referencing this projects:** [https://oshwlab.com/srivad/test-project](https://oshwlab.com/srivad/test-project) As these images show, 1. Vias that should be connected to the 3.3V plane are not 2. The GND vias are connected to both the GND and the 3.3V planes! ![image.png](//image.easyeda.com/pullimage/esw7AhBUBwR3x9kjhQP9pxAItw43IioOO6yxW3sm.png) ![image.png](//image.easyeda.com/pullimage/Y0YDkevdTwqZndqf3YruYcvkp2p3NPpCdKIu1vis.png) **Also note:** 3\. When routing and then pressing the 2 key a warning that changing layers to a plane layer is issued in the lower right hand corner\.     But, when routing and then pressing the 3 key no warning is issued. 4\. When first creating a new 4L PCB\, a spurious GND ratline appears to the lower right corner of the board outline: ![image.png](//image.easyeda.com/pullimage/SgYmG8eE5cETxwQnbGha01NVPDLwfPMrlX1UWQy9.png)
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srivad 2 years ago
@andyfierman Thanks for looking into! @UserSupport - Hi, Since this bug makes 4L designs actually dangerous (as @[andyfierman](https://easyeda.com/andyfierman) pointed out in point 2, GND and V3.3 are connected resulting in a short), I'd very much appreciate your ETA on fixing this.  Thanks.
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UserSupport 2 years ago
That should rebuild plane zone after place vias, and it will be checked at DRC checking. I open this PCB found two plane layer are GND net, no 3.3V 4, 4. When first creating a new 4L PCB, a spurious GND ratline appears to the lower right corner of the board outline: this is the plane zone join the ratline since v6.4.31
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andyfierman 2 years ago
"I open this PCB found two plane layer are GND net, no 3.3V" When I open: [https://oshwlab.com/srivad/test-project](https://oshwlab.com/srivad/test-project)<br> <br> I see two plane layers (not copper areas): one, (2), defined as GND, the other (3) defined as 3.3V. ![image.png](//image.easyeda.com/pullimage/lVpwCthB5PrEW9vhEXPOVCLUeiGS8I0LirxWQIK8.png) I have tried rebuilding this PCB from new with different plane and net names (GND and VCC) in case it was a problem with illegal characters in the 3.3V net name but the result is the same: the VCC plane layer behaves as if it is the GND plane layer.
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andyfierman 2 years ago
Here's my own version: ![image.png](//image.easyeda.com/pullimage/S0dqb05Vb8fRvk12BMw02XAR0cBBEuhv6NPriQCW.png) <br> ![image.png](//image.easyeda.com/pullimage/LI1eUslNGYWx2KPezawQ2kfkb12R1yVZI1nwzyQs.png)
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srivad 2 years ago
@UserSupport Were you able to reproduce the scenario?  Anything I can do to help move this along?  Thanks.
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UserSupport 2 years ago
@andyfierman @srivad rebuild the plane zone? if disable the Auto Rebuil Plane Zoom option at Setting, you need to rebuild it manually , hot key shift+b or ![图片.png](//image.easyeda.com/pullimage/qDexyUGsKAeOtCv8vY1vpuJpj4RzCHT7XhfPe93i.png)
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UserSupport 2 years ago
@andyfierman @srivad rebuild the plane zone? if disable the Auto Rebuil Plane Zoom option at Setting, you need to rebuild it manually , hot key shift+b or ![图片.png](//image.easyeda.com/pullimage/qDexyUGsKAeOtCv8vY1vpuJpj4RzCHT7XhfPe93i.png)
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andyfierman 2 years ago
@UserSupport, The problem described in this Bug Report is with a 4 layer PCB with two inner PlaneZones: GND and VCC (or GND and 3.3V in the OPs original example project). There is no such function as Rebuild Plane or SHIFT+B for PlaneZones. Those functions only apply to Copper Areas. This PCB does not use Copper Areas.
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andyfierman 2 years ago
@UserSupport, Please study the OPs original project: [https://oshwlab.com/srivad/test-project](https://oshwlab.com/srivad/test-project)
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andyfierman 2 years ago
@UserSupport, The Rebuild Plane button that you point to: ![图片.png](https://image.easyeda.com/pullimage/qDexyUGsKAeOtCv8vY1vpuJpj4RzCHT7XhfPe93i.png) only applies to planes on the top and bottom layers made using Copper Areas. It has no effect on inner layers set to planes.
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