WINC1500 is a **Schematic Symbol**. You need to tell us which **PCB footprint** you are asking about. If I search for WINC1500 in the Search Libraries I get: 6 different schematic symbols in the library which between them call up 3 different PCB footprints (two of which have been given identical names of AP9-00127: symbols and footprints must have unique names):  3 different PCB footprints none of which are the AP9-00127:  If I search for AP9-00127 I get 2 PCB footprints:  from which I can see what I assume is your PCB footprint. The cineas footprint has mistakes in it in that it has a large area defined as Board Outline on the right hand end. This is meaningless and should not be present in a PCB footprint anyway. In your version you have deleted that Board Outline area. I think if you follow this procedure your DRC errors will go away (and if they don't you can check and then ignore them): 1. delete your copy of the cineas footprint and then; 2. clone the cineas footprint again **and** rename it as **AP9-00127-cp** (or something to distinguish it from the original) **and** add a Description **and** links to the the WINC1500 manufacturer's (Microchip) and/or supplier's (RS-Online, LCSC or whoever) device and datasheet pages - including the mechanical and PCB footprint dimensions - **and** add some useful tags to it before you save it; 3. make a note of the positions and the outer and hole diameters of the 9 pads the square centre pad; 4. delete the 9 vias in the square centre pad; 5. create a circular multi-layer pad of the same outer and hole diameter as the vias; 6. place it in centre of the square pad; 7. assign it the pad number 29; 8. place 8 more circular pads of the same dimensions in the same positions as the vias were; 9. assign each pad the same number 29; 10. save it; 11. edit the Package attribute assigned to the WINC1500 schematic symbol in your schematic to **AP9-00127-cp**

@andyfierman Yo Andy,  Thank you!  Thanks for digging deeper AND filling in my explanation holes. Thanks for providing clear AND concise instructions.  Thanks for responding. Thanks :) BTW, the original footprint pads (AP9-00127) are slightly off (typically, less then 10 thousands of a mm, so not much).  Simplified my schematic and footprint by 1) removing unused/unneeded pads, 2) shortened silkscreen so to be able to place part against edge of board, pre spec, 3) Added antenna symbol, 4) eliminated boarder, 5) eliminated part ERRORS :)' Should I make this resource (symbol/footprint) public?  Duplicate symbols will get confusing... let know. thanks again, ChrisP.

"1) removing unused/unneeded pads," Careful with that. You may end up compromising the heat sinking from the chip to the board or possibly inadvertently messing up the grounding. Best make the footprint exactly to the manufacturer's datasheet. Your copy of the symbol and/or footprint are automatically publicly available. All user contributions are. That's why it's so important to properly name and document symbols and footprints.   Symbol and creation and association seems to be the part of EasyEDA that people struggle with most. I'm part way through writing a detailed how-to for symbols and footprints but it's going to be another couple of weeks before the first draft will be ready to put up as a How-to Project.

Sorry miss-send... Footprint and Symbol creation and association seems to be the part of EasyEDA that people struggle with most.

In the meanwhile, this should help too: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f)

OMG Andy, lol, that's way to much reading!   Nobody reads or writes (twitter - 150 chars) any more, it takes to long :)   Make a video on how to make a voltage divider, (circuit, footprint, layout, DRC (inject n fix errors), gerber-generation), as it will provide ALL the information on ALL the required steps.  IC's just add more of the same stuff, but looks cooler and fancier.  Remember to KISS it.  Being new to EasyEDA, I got lost "connecting part schematic to part footprint" and then there's your "pad in pad trick" - nice trick!!!  You showed me the "connection" on the right sidebar under Package type.  I missed that-sorry!  A lot of times its terminology too (join vs. merger vs. blend,...).  I can tell you from 30 years of Engineering experience, Engineers play with shit first (turn nobs, try this, try that) - then read.  They don't read first - where's the fun in that!    My suggestion, dump the verbiage, go video and remember to always KISS it (Keep it Simply Stupid)... cp out. Oh BTW, I disagree with your manufacturers footprint statement.  If a pad says "NO CONNECT", what exactly does that mean?  And if protocols are not supported (I2C/UART), why waste the solder paste and risk manufacturing relating issues.  As for thermal conduction, which requires mass (that's what the center ground pad is for, it's 3.7x3.7mm vs. pads 0.8x0.8mm) or flow (air/water,...).  Plus, less pads makes for an easier layout.  My 2 cents, cya...

I agree about the way engineers learn through playing with their new toys. The trouble is that many of the users of EasyEDA are not engineers and do not play to see how the tools work. I'm astonished by how many questions come up that a few minutes of "what does this do" or "let's see how that works" would answer. I agree also that people do not read. I have a problem with that because it's easy to convey superficial "how-to" stuff in videos but it is really hard to explain the "why it's done that way" in a video. If people aren't prepared to take the time to learn the deep stuff then they don't get the why underpinning a lot of the how-to stuff and then post into the forum with questions that otherwise wouldn't need to be asked. I'm also astonished by how many questions come up without any effort by the questioner to try to answer the question themselves. Hey ho.

I worked as an FAE for years, I can't tell you how many times I cut-n-pasted datasheet verbiage because people did read the datasheet or even try!  So I understand your pain, lol:) But back to our hole scenario...  I'm having issues with your pad-in-pad trick... ug! 1) A Via is a fixed pad size, fixed hole size, plated. 2) A Pad is a variable pad size, variable hole size, plated. 3.) A Hole is no pad, variable hole size, plated/unplated. I get Via to Pad errors using #1.  I get Pad to Pad errors using #2.  I'm trying #3, as a Pad, with pad size = hole side, is just a hole - right? With all of the above scenarios, my Net-List (Nets) always has an issue with GND and I can't figure out why!  Everything is connected correctly,  I'm stumped.  Please help! Added you to my project, so hopefully you can look at it.  If not, any suggestions on how to resolve? Thanks, cp.

... never mind.  Started a new project and things appear to working normally.  Original Project database must have gotten corrupted (all the learning/changing), because the language changed automatically.  Anyway, got language changed back, started a new project, all is good.  I think the Russians have hacked you :)'

@chris_2470, Glad you're sorted!