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Vias to other layer eg. GND not recognised
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FrankCA 6 years ago
**BUG** Concise problem statement: Vias connecting top pads of SMT components to bottom GND plane are not recognized. Ratlines dont go away. See screen grab below. Steps to reproduce bug: 1. Place SMT component eg. cap 1206 on top layer with one pad assigned to GND net. 2. Create GND plane pour on bottom layer. 3. Manually place via on cap GND pad and assign via to GND net, or create a trace from pad and switch layers along the way thereby creating a via to GND plane. Results: Ratlines showing missing GND connections still appear indicating SMT pad has not been connected to GND layer, even tho via has been placed on the pad and explicitly assigned to GND net in Via Properties box, or a manually routed track with via has been created. NOTE: I have not tested this for layers other than GND on a 2-layer design, so I'm assuming the same problem may appear for multi-layer designs. And yes, I have refreshed the copper pours by clicking on Rebuild button for each one. ![Ratlines even tho manual vias have been placed][1] Photo view of bottom layer shows via pad is connected to GND plane meaning Gerber file is correct. ![Bottom layer GND plane photo view][2] Netlist shows error (red cross) for GND net and ratlines still remain. ![Netlist error for GND net][3] Expected results: Connections created by manual vias to other planes must be recognized as valid. Browser: Chrome [1]: /editor/20171022/59ec8da7d6eeb.png [2]: /editor/20171022/59ec8de9e322d.png [3]: /editor/20171022/59ec8e34b21e7.png
Comments
maciej.janowski 6 years ago
I've got the same problem. Good to know the Gerber files are OK.
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Tutorials 6 years ago
@maciej.janowski Hi, It is a known issue, we will try to fix it. you can ignore it if your gerber is correct.
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Matthew Thomas 5 years ago
Just curious what the status is of this bug, and what workarounds exist? I think I'm running into this issue, unless the bug has been fixed.
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andyfierman 5 years ago
@thomat65, Have you tried the steps described in the original Bug Report? I don't see a problem with Ratlines in my projects: ![image.png](//image.easyeda.com/pullimage/58wszhOpNBHJEUplBF3nlgfSOA9Ov4j105NlfsQz.png) ![image.png](//image.easyeda.com/pullimage/aF99YIJWfLmjn4NA6czWBpKHCGGVWb0jWNPo0VES.png) ![image.png](//image.easyeda.com/pullimage/KNxQU8UeV53m1EpiRwIyItfoL1Oe7H5KaGtC4G1X.png)
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cjohnson 5 years ago
I think the problem lies within placing a via on the pad itself. Here's a sample project that recreates the issue: [https://easyeda.com/cjohnson/via-on-pad](https://easyeda.com/cjohnson/via-on-pad)
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cjohnson 5 years ago
In practive, it is generally not a good idea to place vias directly on the pads, unless trying to dissipate heat to a separate layer or space constraints on BGA components.
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andyfierman 5 years ago
@cjohnson, I will have another look at that particular situation but in the meanwhile, I can't remember if I have already mentioned this to you in an earlier forum topic: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)
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cjohnson 5 years ago
@andyfierman Yea you've mentioned that to me in a comment before and I've used that method to create thermal planes for PCB components in my designs. I think what the OP is trying to do is insert vias, in the PCB layout to connect a pad to another layer without traces. That will throw a DRC error, and because of that the net will also throw an error.
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