@andyfierman , please to explain copper planes to aluminumpark aluminumpark , you can google it first and check this https://en.wikipedia.org/wiki/Copper_pour out.

The question of when and where to use ground and supply planes is part of a much bigger subject area of circuit and PCB design known as EMC, Signal Integrity and Power Integrity. The following are a very much condensed set of notes suitable for a beginner and for the types of PCB that people are likely to be designing in EasyEDA: **When to use ground and supply planes:** 1. When you need a low impedance path between all points connected to some particular net. >Examples are for high current supply and signal paths, fast switching in switch mode power supplies, high speed digital and high frequency RF PCB layouts. >A well planned plane with few tracks interrupting it and covering most of the board area can give a low impedance path between all the pins connected to the net assigned to the plane. The net is usually a power supply such as VCC, ground or a negative rail. >A poorly planned plane with many small areas connected by thin stretches of copper may have little useful effect and offer negligible improvement over simple, routed tracks; 2. In a multilayer PCB when the layer spacing between adjacent power and ground planes can be kept to very small dimensions (typically less than about 0.254mm / 0.01 inch) so that they form a distributed high frequency decoupling capacitance; 3. When you need large areas of copper to act as a heatsink; 4. A copper plane flood can help even out or balance the copper distribution on a PCB to improve the manufacturability. **Where to put ground and supply planes:** >For 2 layer through hole PCBs the ground plane normally goes on the top layer with traces routed through it with the supply plane(s) on the bottom layer. For 4 or 6 layer PCBs with components on the top layer (layer 1), the ground plane is often placed on layer 2 and supply plane(s) are often placed on the layers (3 or 5) directly above the bottom layer (4 or 6). >However, depending on the application and the effort put into the PCB design, a more advanced 4 layer design with improved signal intergrity, is to put tracks with a supply plane flood on layer 1, a ground plane on layer 2, supply plane(s) on layer 3 and tracks with a ground plane flood on layer 4. This can give useful distributed supply decoupling capacitance on a PCB where normally the spacing between layer 2 and 3 would be too far apart for any significant capacitance between them. Even better, if layer 4 routing allows enough proportion of the area to be used, is to put ground on layer 3 and then signal tracks and supply planes on layer 4. Then whenever a track has to swap from layer 1 to layer 4, just put a couple of ground vias as close to the signal via as possible. That way all of the signal tracks travel across unbroken ground planes and have a couple of ground vias close by to allow the return currents to swap between the grounds on layers 2 and 3 as close as possible to the signla path. >Similar techniques can be applied to 6 and even higher layer count PCBs but this is getting rather deep into design for EMC and for Signal and Power Integrity now... >It is worth considering that even for the simplest two layer PCB layout, adding ground and power plane floods can (a) simplify routing (because, at least in EasyEDA, you don't need to route nets to pads connected by a flood assigned to that net: as long as the plane can reach them, it connects them anyway!) and (b) it hugely simplifies the task of placing decoupling capacitors, routing high current paths and helping to heatsink any of the more power hungry devices. An example of this is the PCB layout for the EasyEDA "Tesseract" Guitar Practice Amplifier: ><https://easyeda.com/example/Tesseract_Guitar_Practice_Amp-MjP71jBni> For more information I can recommend: * <http://www.hottconsultants.com/tips.html> >especially item 10; * Anything by Rick Hartley: ><http://www.ultracad.com/articles/hartley2000.pdf> ><https://www.jlab.org/accel/eecad/pdf/050rfdesign.pdf> * Anything by Dr. Howard Johnson: ><http://www.sigcon.com/Pubs/misc/fund-pcb.htm> *"Anything I should do to make sure my traces don't ground or short to Vcc? "* EasyEDA has dynamic Design Rule Checking (DRC) so keep an eye out for visible warning crosses from this. EasyEDA will create clearances around all traces, pads, planes etc as set up in: >**Super Menu > Miscellaneous > Design Rules Setting** For most purposes the defaults should be OK but if you are routing high voltage then you will need to increase the clearnaces around those routes. Also, check the Design Manager tab on the right hand panel as you go along and at the end of the PCB design and lastly, you must check the Gerber files as they can show up things that you may miss in the busier screen of the PCB editor. *"or is it as simple as laying out the board, running the traces, and creating plane areas on the top and bottom of the board with the right nets?"* As long as you remember to: 1. assign nets to the planes; 2. build the plane areas and rebuild them after any changes; 3. make the plane areas visible; you should be OK. :)

Wow thanks! That is super helpful. Is it a best practice to always use ground and Vcc planes? What do you consider to be high voltages in this case. My board has 40VAC on it in some places but rect/regs to 5V for the ICs. Is there any drawback to increasing the clearances around the planes to 20mil? I'm going to be hand soldering the surface components onto the board for the first set of prototypes. My thinking is that more clearance will prevent any accidental shorts.

* Is it a best practice to always use ground and Vcc planes? Yes. There will now be a storm of people saying that's not true and that there are all sorts of reasons not to. After going on several courses by people who literally wrote the rules about design for EMC, Signal and Power Integrity, I think I can safely say that there is never a situation where having ground and power planes is a bad idea. They can be badly designed - for example by putting breaks between different power planes where tracks carrying fast edges have to cross them - and can be misued - such as by not allowing enough separation between plane edges or planes on different layers either for high voltage insulation or to minimised high frequency coupling between them but that is getting into somewhat esoteric territory and does not alter the fact that planes are never a bad idea. Another misuse of a copper flood is where it is unconnected to anything. Then it becomes an unintentional capacitor which may then couple things that you don't want to be coupled. * What do you consider to be high voltages in this case. The clearance depends on the voltage. Simple as that. http://www.smps.us/pcbtracespacing.html http://www.smpspowersupply.com/ipc2221pcbclearance.html AT present, there is a limitation in EasyEDA in that the same set of design rules apply across all signals on the board. More advanced EDA tools like Kicad and gEDA allow "classes" of signals that each have their own design rules, including their minimum clearances, trace widths, via sizes etc. What this means is that you may have to change the design rules as you route the board to allow the dynamic DRC to pick up any errors as you go along and then step through different DRC setting as you check the board at the end so that different clearances etc., show up with each set of checks. Tedious but classes are some way down the EasyEDA ToDo list yet. * Is there any drawback to increasing the clearances around the planes to 20mil? See above but note that as the clearance increases more of the plane may get pinched off into islands (set **Keep islands** to `NO` in the Copper Area Properties. See comment about unconnected floods.) * My thinking is that more clearance will prevent any accidental shorts. That's why the outer surfaces of the PCB are covered in a thin, heat resistant, insulating coating of what's called solder resist. It should be all over the top and bottom surfaces board except where there are pads. In a well designed board with well designed footprints, the resist should extend between each pin, even of parts with a fine pin pitch. Resist pretty much stops any accidental solder bridging. It won't stop you accidentally soldering adjacent pins together but it makes it much less likely and easier to recover from. The other thing that helps is the best quality soldering iron you can afford! And for SMT parts, with a short handle to tip distance. :)

Wow thanks again! That helped a ton and helped me really understand a lot better. I'm ordering my first board right now!

Hello. I am designing right now a 2 layer pcb. And i already finished my traces except for the ground and vcc planes. Can i ask where can i find or how can i add these?. Or it automatically added when i put a copper on a board?

[https://docs.easyeda.com/en/PCB/Copper-Pour/index.html](https://docs.easyeda.com/en/PCB/Copper-Pour/index.html)

If I add a copper region and assign it to the GND net, is it supposed to automatically connect the GND traces to the copper region? In my case, the GND rats nest lines are still unrouted, and I don't see a way to connect them to the copper region.

If you don't explicitly route the GND nets then, when you apply a GND copper area, the GND nodes may still show ratlines but they are still connected by the copper area. If you save the PCB, close it and re-open it, then the ratlines should not be shown. If you do explicitly route the GND nets then when you apply a GND copper area then the GND ratlines will be removed.

@dillon well, I Googled and find this website :o And when I google it again, I am back at this website.

I am having a 4 layer pcb from very old pcb layout software which doesn't run any more. GND plane as 2nd, +5 plane as 3rd. Due to a 24v relay an area of the +5 plane needs to be connected to that so I add a Solid with +24 net. The weird thing is that it shorts all pads, it does not add clearance around pads so everything is shorted. For some areas I need to remove +5 and gnd copper so also use SOLID for this without a net, but then it removes everything including signals and pads. I payed a designer to fix it and he delivered it back, I can still see the gerber is shorting everything and not adding proper clearance to pads and signals. But he just say that I should not worry about clearance warnings and shorts. That does not make sense. I understand that a solid is a quick way to connect a lot of pads with the same net but shouldn't it add clearance to those pads without the same net? Is there a hidden setting to define clearance for solid areas?

@gilvader, I suspect you or your contractor should be using Copper Areas with the Copper Area Manager rather than Solid Regions set to Solid or set to No Solid but what you describe sounds too complex to understand properly without more information about your project. It would help us to help you if you can you post some screenshots or share it as a public project or add me to your team so I can have a look?