Your question is ambiguous. Do you mean: 1. Avoid autorouting to vias on specific nets that are already placed in a PCB; 2. Avoid placing vias whilst autorouting particular nets, i.e. route on one layer only without changing layers?

Sorry for the confusion. 2 is what I meant.

Maybe my question should be: what size of vias is just as safe as no vias for a current of max 2 Ampere.

Hi Frank! It should be better to publish your project to see how the full scope of the project to determine how much vias you need for your project. I'm happy to help with the design aspects of your project. Regards, Markus Virtanen HW / Electronics Designer

Thank you Markus! I made the project public. Do I need to share an url? The project is called ‘switchbox‘

@FrankRoozendaal, please post the whole oshwlab url.

[https://oshwlab.com/FrankRoozendaal/switchbox](https://oshwlab.com/FrankRoozendaal/switchbox)

I managed to remove some vias. Is a good starting point to make the via drill size as large as the trace width and the via diameter twice the drill size?

The calculation of via size and number vs. current vs. temperature rise is not simple. For circuits where the high frequency behaviour of vias can be ignored, the basis rule is to make the total cross sectional area (csa) of the through plating of the vias equal to the csa of the traces in which they are placed. You can obviously have a few large diameter vias or a lot of small diameter via to reach a given csa. So you need to know the minimum thickness of the through plating and then do some cylindrical geometry to work out the same of the little solid copper cylinders that it forms. If the drill diameter is D and the plating thickness is T then the plated hole diameter, d, is (D-2*T). The csa is therefore the area of the circle of diameter D minus the area of the circle of diameter d. This _may_ be a reasonable calculator but read the posts to satisfy yourself. [https://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/](https://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/)<br> <br> The heat sinking of the surrounding substrate material and the attached traces is more complex to deal with: [https://resources.altium.com/p/pcb-current-carrying-capacity-how-hot-too-hot](https://resources.altium.com/p/pcb-current-carrying-capacity-how-hot-too-hot)<br> <br> Skin effect and other aspects of the complex impedance of vias complicates the issue at high frequencies but is unlikely to be a consideration for most projects undertaken on EasyEDA.

Thank you for the information.