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bug or feature?
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boxxofrobots 6 years ago
**BUG** Here is the board. It is a common array of 28 pin jedec devices. This sort of chvron layout is trivial to execute with tape and mylar, yet the autorouter seems to have no awareness of how to identify these layouts or to route them optimally. This board is proving very tedious to get through the autrouter, and it is a 4 layer board. I do not know if this is a bug or a feature request. https://easyeda.com/editor#id=b783012708f34d248ff53d97a9cdff60|3232f00ed270489fa73a68305cd4c37d|329c2fb8d3574840a4ac996b137bf6e7 Browser: FF
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Tutorials 6 years ago
Can you give us a picture?
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boxxofrobots 6 years ago
Here is the way your router tries to route memory arrays. This frequently fails because your router is unable to see memory arrays as memory arrays and puts the chevrons right against the pins (why do you do this, anyway?). ![enter image description here][1] [1]: /editor/20170716/596b1bcf6787a.png
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boxxofrobots 6 years ago
Here is the way memory arrays should be routed. Having the extra space in there allows the router more freedom, yet in spite of this it suddenly cannot route this board at all. It says "finished successfully" but the board is littered with ratlines over what should be simple routes.![enter image description here][1] [1]: /editor/20170716/596b1c7142e6a.png
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Tutorials 6 years ago
The autorouter is not good enough, We don't suggest using this option for complicated PCB.
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