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clearence error
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GastonMelo 5 years ago
DRC clearence settings is 3.937 mil, track width is 3.94 mil ![clearence_error_2.png](//image.easyeda.com/pullimage/rYfq5nG6Hs9hW61MPMtvW2UxWeNNMuh2X4jDw9iZ.png) ![clearence_error_3.png](//image.easyeda.com/pullimage/TH42sI0BX7cK2Lx6776taeChH1zX4iKXKuX1sRCn.png) If I remove the Top Layer, the topPasteMaskLayer and the topSolderMaskLayer the DRC checking shows not errors. Why? If I enable one of those 3 i got 8 error clearence (the same number as vias). Gastón
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andyfierman 5 years ago
Check the DRC errors under the Design button in the left hand panel. Maybe the diameter of the copper annulus of your vias is too large? If you intend that the 8 vias should connect to the GND copper area then you might want to read: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)
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GastonMelo 5 years ago
![clearence_error.png](//image.easyeda.com/pullimage/FZBdTo48DuhvcxKA2stLEmXJlLN8Ai4krXWzCxO5.png) the GND copper area is in the package of the Ic (by default). Could I just ignore this errors?
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GastonMelo 5 years ago
solved!!! click on un vias and set as GND. Thanks Gastón
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