The same thing happens with a normal header pin hole, so I think it must have something to do with a setting, rather than the packages

I am not realy clear this problem, @andyfierman  Andy can you help?

You can see in this snapshot that the blue layer net is directly attached to the pad. There is also red trace coming from the same pad and going to another pad. The extra trace shouldn't be there as the multilayer pad has a number of vias connecting each of the layers. 

Really hoping to get some help with this problem.

Hi Do you mean this ratline?  It is a know issue, you need to route a track to connect this net.

But if the pad is connected (spoked) to the net on another layer (shown in the blue in both the screen shots), why does another track need to be made?

There are 3 layers in this design. on the pad you show, the red is GND and the blue is BATT_IN. The bottom layer of the pad is spoked to the bottom net, and the top layer of the pad is isolated from the top net, the 2 layers of pads are connected by vias, but the program still wants to connect the top pad to another pad that is on the same net. I don't understand. Is this a known problem? Can I just ignore those ratlines instead of creating a useless track?

@geekness Yes you can ignore it, but you need to check the Gerber after the design.

@geekness, I am confused by your statement: "There are 3 layers in this design." The project that you have linked to is a 2 layer PCB: Top and Bottom layer only. There are no inner copper layers. If you click on one of the pads you are asking about - without the extra track that the ratline implies that you need - and then click H to highlight the whole net, you will see that everything that you expect to be connected is indeed connected. So it is OK to ignore these particular ratlines. Please, however, see (4), (5) and (6) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f) It is **essential** that you check your Gerber files before submitting the PCB for manufacture. I recommend using gerbv: [http://gerbv.geda-project.org/](http://gerbv.geda-project.org/) [https://sourceforge.net/projects/gerbv/files/gerbv/gerbv-beta/](https://sourceforge.net/projects/gerbv/files/gerbv/gerbv-beta/) Note that you are getting a warning that "Copper Area do not allow self-intersection!" Please check this warning.

Ok, thanks for the reply. I will also check out gerbv.