Your project is private so only you can see it. Please (1) read: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) * The PCB Footprint for this part: [https://lcsc\.com/product\-detail/Electret\-Condenser\-Microphone\_Goertek\-B4013AM423\-008\_C233794\.html?ref=editor&logined=true](https://lcsc.com/product-detail/Electret-Condenser-Microphone_Goertek-B4013AM423-008_C233794.html?ref=editor&logined=true) is incorrect and I have reported this footprint to be in error. "Inner pad 1 must be multilayer pad with small hole. Outer ring must be pad not solid region. The small top layer pad 2 is surrounded by this solid region and connecting to it generates a DRC error."

I failed to copy and modify the pcb layout for the part. My project uses the part for C233790, which has a similar problem, but slightly newer part with better sensitivity. To connect the outer ring, I layed some track and moved the layout until the outer circle touched the track. For the inner connection I placed a via in the middle and connected it. I get a DRC clearance error for the outer ring.  I presume I can ignore this. I have made the project public. it is [https://easyeda.com/Peterg17/micamp](https://easyeda.com/Peterg17/micamp) Do you think I can get this pcb made as is?

In datasheet: [https://datasheet\.lcsc\.com/szlcsc/1809140716\_Goertek\-B4013AM423\-093\_C233790\.pdf](https://datasheet.lcsc.com/szlcsc/1809140716_Goertek-B4013AM423-093_C233790.pdf) I think that there is a mistake with how the land pattern is shown. The inner 0.9mm diameter circle in Figure 10.1 (indicated by the little hand) is shown white. I think that it should coloured in yellow to show that it is a copper pad. 

I have notified LCSC of this drawing error so that they can contact the manufacturer.

In fact Fig 10.1 in: [https://datasheet\.lcsc\.com/szlcsc/1809140716\_Goertek\-B4013AM423\-093\_C233790\.pdf](https://datasheet.lcsc.com/szlcsc/1809140716_Goertek-B4013AM423-093_C233790.pdf) should be like Fig 11.1 in: [https://datasheet\.lcsc\.com/szlcsc/1809140716\_Goertek\-B4013AM443\-058\_C233795\.pdf](https://datasheet.lcsc.com/szlcsc/1809140716_Goertek-B4013AM443-058_C233795.pdf)

@Peterg17, If in your PCB, you edit the Package attribute of  MIC1 from: MIC-R4.0-2P-SMD to: MIC\-R4\.0\-2P\-SMD\_NO\_DRC\_ERRORS  then click **Update** and then do **Update PCB...** your PCB will then pull in a PCB Footprint that has no DRC errors: 

The above modified version of the MIC-R4.0-2P-SMD PCB Footprint complies with the requirement that to avoid DRC errors when connecting to a PCB Footprint, everything copper in it must be made of Pads and not solid regions etc. Please see: [https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints](https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints)

Hi. I found your part "MIC\-R4\.0\-2P\-SMD\_NO\_DRC\_ERRORS" in libraries\-\>pcb libs\, installed it in my schematic\, after deleting the original part\, saved it\, and updated the pcb\. Unfortunately, it refused to connect pin 2 directly, and if I force it by moving the footprint over a preplaced track, it now gives about 5 drc errors, instead of the single clearance error previously. Kindly check the pcb in  [https://easyeda.com/Peterg17/micamp](https://easyeda.com/Peterg17/micamp) I checked out the "avoiding-drc-errors-in-footprints" document, but perhaps it is an unfinished document? I cannot find anything explanatory there. I will continue to try anything you might suggest. I appreciate your efforts so far. Apologies if I have misunderstood anything.

You need to update the Package attribute of the symbol for MIC1 in the schematic:  (Don't worry about the ratline showing an apparent connection of Pin 2 to Pad 1. This is a bug where a connection is assumed to be in the centroid of the pad which for the ring Pad 2 is in the geometric centre and so coincides with the centre of Pad 1. You'll see when you place and wire to the footprint that it sorts itself out!) and then do **Update PCB...** to bring the new footprint (which you have just assigned to the symbol in the schematic) into the PCB. In the **PCB** you also need to then: 1. delete the via on the MIC end of the ELECTRET track; 2. rotate the MIC1 PCB Footprint by 180 degrees (select > R key > R key) to put the Pad 2 attachement node on the outer ring onto the right side to connect to the COM track;  3. reroute the ELECTRET and the COM tracks to ensure they properly connect to the new pads in the new PCB Footprint. * Recommend you read: (2.3) in (2) in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a)

Forgot to say: I've modified the footprint to replace the multilayer pad in Pad 2 with a Top layer pad. It was causing a DRC error because it had an outer diameter of less that the 0.6mm JLCPCB minimum for a 2 layer PCB. :)