Home>Forum>Topic
Latest Topics Latest Replies EasyEDA Std EasyEDA Pro JLCPCB LCSC OSHWLAB General Discuss
Schematic PCB Simulation Skill Extension Feature Requests Bug Reports
You need to use EasyEDA editor to create some projects before publishing
removable ratelines
344 2
Program Tuber 4 years ago
users must be allowed to remove selected ratelines which ruin their projects
Comments
UserSupport 4 years ago
It is not a bug. you just need to remove object's net name.
Reply
andyfierman 4 years ago
Before anyone goes round removing ratlines because they appear to "...ruin their project" it is important that they understand what ratlines represent and therefore what they are doing when removing them. Please read: [https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d](https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d)r
Reply
Login or Register to add a comment
goToTop
你现在访问的是EasyEDA海外版，建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程，下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus-@1x -mockplus-

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice