Is this bug or feature? When I design PCB with default parameters and run DRC it will give error of all vias.
Looks that default via size is 24mil and DRC diameter is 42.016mil. So is that DRC diameter some kind rounding error?
![image.png](//image.easyeda.com/pullimage/DqnQamhzRYcwdiRHF9gCCsc0vf2wSMsTfttMLxZD.png)
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