Please make your circuit public and post the link to it so that we can see it to help diagnose the problem. Thanks.

@andyfierman [enter link description here][1] thank you andyfierman [1]: http://easyeda.com/editor#id=sR9FXf9rJ

@andyfierman we are working on communication tower circuit so its very difficult to calculate the effective resistance....by using easy eda the circuit is getting more complicated ..so plzz help us out in this

OK, I can't see what the problem is in: http://easyeda.com/editor#id=sR9FXf9rJ but there are some things that are a bit strange about your circuit. 1. The right hand end of most of the horizontal resistors (such as R422) - except R1, R86, R143, R184 - haas a short section of polyline drawn in. This should have no effect on the circuit but is a bit confusing when trying to check connectivity. 2. You have many overlapping wires. In other words you have drawn two wires overlapping between the same nodes. Again, this should have no effect on the circuit but is a bit confusing when trying to check connectivity. Some wires overhang the ends of the component pins. (See this thread for more: https://easyeda.com/forum/topic/RED_Dot_or_No_Dot-zrlf9qkCw) 3. If you look at the Design Manager you will see that the first entry for the Nets has a red error marker. Unfortunately the Design Manager gives no further information about what this error is. If you click on any entry in the Design Manager the display zooms in to that component, net or - if in a PCB - DRC error. If you click on the red error marker, the display zooms into empty space. There is obviously something there that is invisible. In fact if you do a CTRL+A and then move the whole schematic down the canvas, some unconnected wires will come into view in the upper left hand corner. If you delete these and refresh the Nets section of the Design Manager, the error will be gone. 4. It is not possible to generate a spice netlist from your schematic. This is why it is not simulating correctly (although why you see the "Simulation too large error" is not clear). It is not clear if the circuit too large warning is what is stopping the spice netlist generation or if the failure of the spice netlist generation is what is causing the simulation too large error. I am raising this with support to try to resolve the cause of the failure to generate a netlist. If you can generate a netlist then you could paste it into: http://www.ngspce.com and try to run the sim in there. Alternatively, you can run the netlist in LTspice: http://www.linear.com/designtools/software/#LTspice LTspice is free and can be run natively in MS Windows and Mac OS X. It can also be run pretty much flawlessly in Linux using WINE. If we cannot get you a netlist from your existing schematic then please try redrawing the circuit in EasyEDA but this time build it up and run it in sections (I suggest horizontal sections) one section at a time and keep copies of the circuits during construction up to the point where you get a successful simulation or you get the "Simulation too large" message. You could then go back and simplify the last complete circuit that worked by using EasyEDA to tell you the resistances between each node of the circit that connects to the next section and simply replace the whole of the circuit up to that point with a simple set of single resistances. Please see: Advanced probing and simulation control https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.4i7ojhp and: Making measurements of simulation results https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.2250f4o for how to measure resistances in circuits. I also have a couple of suggestions. a. If you use parameters then you can easily define the values of your resistors. In view of (b) below, you may also want to consider using expressions too. For information about using expressions and parameters, please see: Expressions https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.sqyw64 Parameters https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.2r0uhxc b. If you are modelling electrical resistances of the physical structure of a radio communications tower, have you allowed for the fact that at the radio frequency of interest, the resistance of the tower structral components will be much higher than the DC resistance due to the skin effect? https://en.wikipedia.org/wiki/Skin_effect (If we cannot get this to work in EasyEDA even after simplifying your schematic as described above, you can redraw the whole thing in LTspice and try it in that.) ![enter image description here][1] ![enter image description here][2] [1]: /editor/20160530/574c5f7197620.png [2]: /editor/20160531/574c6a6859990.png

Here's a way to do it: https://easyeda.com/andyfierman/Metal_tower_resistances-OQJDVBvpH I think this is a neater way to do it and is much easier and faster to build and modify but it is harder to visualise the structure of the tower compared to a schematic representation. I did try redrawing your original schematic, building it up in sections but have discovered a few bugs in EasyEDA that make copying and pasting more than a few components at a time a bit error prone. Even when I corrected all the copy and paste errors, I could only run the simulation for the top 8 sections of the tower. The subckt based version runs all 21 sections (I treat the base(?) of the tower as an array of the same structure as all the others but with a special set of resistor values). I am not sure why this is and will raise this with support. In the meanwhile I hope you can continue with your tower modelling using the subckt solution. :)