The warning looks like this Warning: Dynamic gmin stepping failed Note: Starting source stepping Warning: singular matrix: check nodes nonet and nonet Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful gmin step Note: One successful source step Warning: singular matrix: check nodes nonet and nonet Warning: singular matrix: check nodes nonet and nonet Warning: source stepping failed Transient solution failed - Last Node Voltages ------------------ Node Last Voltage Previous Iter ---- ------------ ------------- u3_1 0 0 r6_1 0 0 r7_2 0 0 r2_2 0 0 u1_6 0 0 volprobe1 0 0 u2_5 0 0 r3_2 0 0 u2_3 -1.03234e-125 -3.9914e-138 r1_1 1.03234e-125 3.9914e-138 nonet 0 0 u1_5 0 0 u2_1 0 0 c2_1 0 0 v1#branch 0 0 doAnalyses: iteration limit reached tran simulation(s) aborted Error(parse.c--checkvalid): volprobe1: no such vector. ngspice-26 done

Sorry but your schematic is not public. Please make the schematic public so we can look at it. In the meanwhile, the warning that you have been given: `Warning: singular matrix: check nodes nonet and nonet` tells you to check the node or nodes labelled as `nonet`. Most likely you have left one end of a capacitor or a current source unconnected. Please see: Every point in a simulation schematic MUST have a DC path to ground: https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.26in1rg

@andyfierman Thanks! I will look into it.

There seems to be no unconnected points in this schematic: [https://easyeda\.com/editor\#id=53f5dc927f39416ba57df6feeff47b89\|5ae0af5565274354b8333508659c8586](https://easyeda.com/editor#id=53f5dc927f39416ba57df6feeff47b89|5ae0af5565274354b8333508659c8586) Why does it also show the singular matrix error? Thanks! I simulate at 100ms for 10s.

@Wetitpig, Your schematic is hard to read. Please see (2) and (4) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f) It has 9 transistors in it compared to the 8 in the circuit that you have referred to in your link: [https://www\.researchgate\.net/publication/256373597\_A\_high\_speed\_8\_transistor\_Full\_Adder\_design\_using\_novel\_3\_transistor\_XOR\_gates](https://www.researchgate.net/publication/256373597_A_high_speed_8_transistor_Full_Adder_design_using_novel_3_transistor_XOR_gates) * Check that you have drawn it correctly. According to Fig 3 in this paper, the XOR structure is entierly driven by the input signals themselves and does not require a dedicated power supply. The possibility of a circuit being powered by it's own input signals is breifly discussed in: ### All simulation circuits MUST have a power and/or signal source in: [https://docs.easyeda.com/en/Simulation/Chapter4-Introduction-to-using-a-simulator/index.html](https://docs.easyeda.com/en/Simulation/Chapter4-Introduction-to-using-a-simulator/index.html)