small holes in traces
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Cameraman 1 month ago
When I create traces they all seem to have small holes in the beginning and ends, how can this be avoided as I don't need these traces to have a hole going through the board to the other side... ![Screenshot 2019-06-08 11.52.35.png](//image.easyeda.com/pullimage/V2RZol13fcvU0kmF53mOR4nDFYk4XrH2OZIN5ppR.png)
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andyfierman 1 month ago
Your project is private so only you can see it. It is not therefore possible to clearly identify what is actually going on. Without sight of your project or a partial copy of it, best guess is that you are placing multi-layer pads with small holes in them. If you need pads on each side of the board but without through plated holes in them then use Top Layer and Bottom Layer pads and via together elsewhere on the tracks connected to them.
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Cameraman 1 month ago
@andyfierman    Thank you...  I've made it public, maybe you can take a look?
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andyfierman 1 month ago
@Cameraman, * Please change the category of this post to **Bug Report**. You can ignore the black dots. They correspond to the start or end of track nodes where you have started or ended each track at a pad. You can see these nodes when you select a track in the PCB Editor. They should not appear in the Photo Viewer but they do: ![image.png](//image.easyeda.com/pullimage/LQad722mjZDEgBiAcLYNNT4eXv1DcD5sQ7dC0t2I.png) ![image.png](//image.easyeda.com/pullimage/Vz5Flp2vaV50xEP6amp2FUkHb8IYLslrtxYaZQhz.png) To be sure, please check your Gerber files using gerbv as advised in the Tutorial.
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Cameraman 1 month ago
Thank you, I was getting worried because I saw them in the photoviewer as well....
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andyfierman 1 month ago
@Cameraman, Understandable. :) Photoview and the JLCPCB Gerber Viewer are still a bit buggy.
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Cameraman 1 month ago
@andyfierman Andy, when I want to generate a Gerber for fabrication, it fails the DRC check complaining that these holes are indeed via's and their diameter is too small...
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andyfierman 1 month ago
@UserSupport, I do not understand what happened to this PCB. Every node of every track (start, end and vertex) appears to have spawned something that appears in the multi-layer layer as the same ident and which is seen as being a 0.61mm via. They do not however appear as vias if visiblity of all except the multi-layer layer is turned off. The ident appears but no physical structure. It does not seem to be possible to select and delete them individually. Attempting to do CTRL+A with the visiblity of all except the multi-layer layer turned off results in all the card edge pads being deleted reducing the DRC errors from 310 to 76 but breaks the PCB at the same time. * Note that this is a PCB that has been created by drawing the elements directly. There is no schematic and the Connect-Pad-to-Pad tool does not seem to have been used.
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Cameraman 1 week ago
Hi Andy, do you think we'll be hearing anything from user support about this issue?
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andyfierman 1 week ago
@UserSupport, Could someone have a further look at this PCB? Thanks.
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UserSupport 1 week ago
@Cameraman @andyfierman This issue should be fixed at previous versions Hi Cameraman At v6.1.52, are you still meet this issue? please export the PCB as EasyEDA file and send to [[email protected]](mailto:[email protected]) I will have a look. Thanks
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