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too short simulation
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filmax 7 years ago
thanks again for the support you give me. I would like you to another question: simulating the circuit called "divisore" I do not go more than 7 milliseconds the simulator crashes and writes me that the simulation is too long. I tried various combinations but I trvato solution. the problem is that the circuit generates a pulse of 100 + 100 us that is repeated from 10 ms to 250 ms. how can I do?
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andyfierman 7 years ago
More later but for now, try placing this directly into your schematic *as a spice directive*: `tran 1u 5m` Then press **CTRL+R** to run it directly. That will get you started but there's something strange because it takes a very long time for the sim to run and I don't know why yet and it is that which is causing the sim too long issue. Read more about putting analyses directly into the schematic here: https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.3fwokq0
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andyfierman 7 years ago
Try editing the names - in the right hand panel - of the 555 timers from `555` to `555_EE` I have added an experimental new bipolar 555 timer model that may be a bit less accurate in terms of output edge speeds and voltage vs. load current but it runs a lot faster and used less CPU resource. (The model can be adapted to a CMOS version if desired.) See what you think. BTW there is no need to load any of the outputs with resistors (or the 100pF on the output of one of the 555 timers. They just add wasted load currents and - in the case of the 100p cap - just add to supply noise which the bipolar 555 is perfectly capable of supplying enough of on its own!
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filmax 7 years ago
@andyfierman Thanks for your help but as you write the spice directive on the diagram? I reduced the scheme by using two gates OR 3 INPUTS but the simulator does not work. Is there any problem with these gates? thank you
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andyfierman 7 years ago
If I run it with *tran 6u 6m* then I get very similar results where your two volprobes as in the version before you replaced the AND2EE followeed by the NAND2EE + INVEE outputs with NAND3EE gates. To add a spice directive in the schematic: Adding the simulation directive directly into the schematic is easy. All that has to be done is to type the directive as a line of text in the schematic and then do: **Properties > Text type > spice** to turn the passive text (blue font) into an active spice directive (black italic font). Note that one and only one simulation directive can be active for any one simulation run. The example below illustrates how to do this: https://easyeda.com/editor#id=a2b920eb01b44c1a8d260666f6f73388 For the background to this please see the whole of: https://docs.google.com/document/u/1/d/1OWZVVFRAe_2NW3WratpkA_SGuHa5AcRow5ZRfvcoVTU/pub#h.4i7ojhp
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