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top and bottom track within component footprints
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jthompson8 1 month ago
the program allows you to add track to component footprints and the track then displays correctly on the PCB the component is placed on. all seams to work fine except the DRC error checking does not account for track on the top or bottom layers of a component footprint and it generates loads of errors saying tracks overlap when they dont and there is not anything wrong. this would be really useful if the RDC check was fixed to account for track within components
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jthompson8 1 month ago
@andyfierman very usual link, thank you
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andyfierman 1 month ago
A way to avoid this problem is described here: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)
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