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top and bottom track within component footprints
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jthompson8 2 years ago
the program allows you to add track to component footprints and the track then displays correctly on the PCB the component is placed on. all seams to work fine except the DRC error checking does not account for track on the top or bottom layers of a component footprint and it generates loads of errors saying tracks overlap when they dont and there is not anything wrong. this would be really useful if the RDC check was fixed to account for track within components
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andyfierman 2 years ago
A way to avoid this problem is described here: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)
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jthompson8 2 years ago
@andyfierman very usual link, thank you
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你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
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