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vague "Incomplete connection, please check." error
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mtroyer 4 years ago
Hi Folks, I am a newbie to PCB design working on my 3rd project with each one getting progressively more complicated.  I am hoping that someone can steer me in the right direction to debug some issues I am having. I am getting the following error on 3 nets when trying to create my gerber file:  "Incomplete connection, please check." Unfortunately, the message is a bit vague so I am not sure about the root problem with each of the nets.  I have recreated them several times to no avail.   The project is published at [https://easyeda.com/mtroyer/esp8266-pir-temp-battery-board](https://easyeda.com/mtroyer/esp8266-pir-temp-battery-board). Any tips on resolving these 3 net issues is greatly appreciated.  Also, appreciate any design tips in general!  My forte is software/firmware programming but I am really enjoying this learning process. thanks, Mark ![image.png](//image.easyeda.com/pullimage/mcg1oLfz2z86eRJyNfQeimCu0slnlMcliOv6yimr.png)
Comments
andyfierman 4 years ago
Turn off visibility of all layers except Ratlines. Look for Ratlines. These are your incomplete connections. :)
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mtroyer 4 years ago
Thank you Andy!  That pinpointed the errors and now all is resolved.   I did not completely understand what a ratline was although I was using them to do my manual routing...
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andyfierman 4 years ago
[https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d](https://easyeda.com/forum/topic/Understanding-Ratlines-371bdbf646c54b23a57451eb05b2026d#:~:text=Understanding%20Ratlines.&text=Ratlines%20do%20not%20represent%20PCB,physical%20routing%20of%20that%20net)
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Zachrey 3 years ago
I have almost exactly the same problem! I turned off visibility of everything except ratlines and there are NO ratlines visible. I left the ground connections of many components such as bypass capacitors unhooked, thinking that the top layer Copper Area (E) connected to GND would take care of those in a jiffy. But do I hafta manually connect all the grounds to make the error go away?
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UserSupport 3 years ago
@Zachrey There must has a ratline, maybe it is too small, please find it carefully, or you can public your project we can help to find out
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Zachrey 3 years ago
@UserSupport I feel uncomfortable making my layout public. Is there a way to do it more discreetly?
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Zachrey 3 years ago
I carefully scanned the board and there are no ratlines. I also manually connected the grounds to all the components that required using vias and bottom layer metal. But the problem persists. It just does not want to recognize that all the grounds are connected.
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UserSupport 3 years ago
@Zachrey You can export your PCB as EasyEDA format and send to [support@easyeda.com](mailto:support@easyeda.com), I will help to check
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Zachrey 3 years ago
OHHH!!! I think I got it! I closed the pcb layout and the schematic files in the EasyEDA Std web portal and then re-opened them. Now there are no errors! I guess it needed to refresh itself by reloading!! Whew! Now on to copper area fill...
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Craig Zych 2 years ago
@Zachrey Thank you. I think that's the second time I found your answer when I had this problem and a restart fixed it.
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