it's especially weird when adding multiple net labels sequentially since, by default, they all get the same name, which is probably almost always the wrong thing to do.
For any scheme of initial and subsequent netnaming, there will be pros and cons.
There's no `right` way to do it.
The philosophy used in EasyEDA is based on **incremental net naming** for the first instance of each new netname to avoid accidentally giving two different nets the same name so shorting them together but then using the **same name** for subsequent instances of the same label because they are assumed to be being placed to join nets without the need to draw the connections as physical wires (usually to reduce the clutter in the schematic).
Sorry, that not quite right.
A better explanation:
The philosophy used in EasyEDA is based on *incremental net naming* for each new instance of a netname placement to avoid accidentally giving two different nets the same name which would result in them being shorted together. This is particularly useful when naming the taps at one end of a bus.
For subsequent copy and pasted instances of a netlabel, *exactly the same name* is pasted because they are assumed to be being placed to join nets without the need to draw the connections as physical wires. This is useful for reducing the clutter in the schematic and particularly for naming the taps at sets of bus entry points other than the first.
yeah, but what i don't understand is why the net label overwrites the existing net name?
for example, i have a component placed, and i can see in the PCB editor that the net name given to the wire connected to one of its pins is "U3_26". when i place a net label on that wire, i'd expect that label to be named "U3_26", not "netLabel7". the "netLabel7" name tells me nothing (except that it's the 7th label placed - which is useless info to me).
as an aside. why isn't it possible to view/edit the names of nets in the schematic editor?
when i select a track or pad in the PCB editor, i can see the net name in the properties (although editing this is broken since it doesn't cascade to connected components). i expected to see this also in the schematic editor.
Ah,
Sorry, I had misunderstood your question.
The short answer is "because that is not how the netlabel function was designed to work".
If you want it to work the way you describe or at least have some way to select an option of having it work the way you describe then please submit this as a Feature Request.
Something that you could include in such a Feature Request is that, instead of having to apply an explicit label to show a net name, it may be easier for the existing nets to be automatically annotated on the schematic in much the same way as happens already in the PCB layout.
Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice