i solved it by removing all net labels (**didn't solve it but that's probably not a good idea)** and recopying  max2 two time and then it was ok. to be blunt, keeping your user netlist intact is the #1 job of an EDA. if anything happen to it, or its not explicit about what its about to connect or not you can have a bad board easily. i'm not a developer or a UX developer, but as it stands that is a major issue needs addressing if i to recommend this (free, thank you) software to others.

there is still some issue, look at R1. it **looks** connected , but its not. ill clone this and leave it for you team [https://easyeda\.com/editor\#id=\|2a2dcbabd75946e7b35d54ce46058509](https://easyeda.com/editor#id=|2a2dcbabd75946e7b35d54ce46058509)

"...can you explain why P3 is connected to P4 and not as the schema shows?" The screenshot of your original schematic shows that the pins of P3 are connected to the corresponding pins on P4. This is because - with the possible exception of the two nets to which you have added a second netlabel to - the set of nets connecting to P3 have the same netnames as the set of nets connecting to P4. This is also true for the CLK and LOAD pins in your screenshot. In EasyEDA, assigning two different netlabels to a net can lead to unexpected netnaming depending on the sequence and the XY position of where the netlables were applied. In any EDA tool, any node with the same netname attached to it will be connected together. If you do a copy and paste of a block of a schematic to the same schematic (even if it is on a different sheet) then any nets that have user assigned netnames will be connected together. If you copy and paste nets without netlabels assigned to them then EasyEDA automatically assigns arbitrary netnames to them so they are not connected together. It is worth considering that you would probably expect the VCC pins to be connected when you copy and paste a section of schematic since it already has the VCC and GND netflags attached to it. Therein lies the EDA tool designers dilema: you would expect some nets to be copied and pasted with their netnames changed in some way to prevent duplication and therefore unintended cross connections however, you would also expect some nets to be copied and pasted without changing the netnames to deliberately ensure continuity.

BTW, if you have a block of circuitry in a schematic ( or a PCB) that you want to copy, if you copy it then paste it into a new schematic sheet and then save that sheet as a **Schematic ( or PCB) Module,** then you can place that block into your main schematic (or PCB) and any netnames will be reset.

thanks andy for the detailed answer, i will cherry pick text from you answer just to highlight what i see as a design/UI issue with easyeda. >  exception of the two nets to which you have added a second netlabel to the fact you **can** assign two netlabels to the same net is bad. as a user i expect a clear warning/sign that im about to change a netlabel for another. leaving two netlabels on the same net, doesn't make sense. one should override the other.  connected to that, each have a different font - might be picky, and probably this are artifacts from me using ready made schematics from a previous module/design. but, i think a little more constraints should be imposed to make the schema cleaner and valid. both to user and netlist. [https://docs.easyeda.com/en/Schematic/Wiring-Tools/#Net-Label](https://docs.easyeda.com/en/Schematic/Wiring-Tools/#Net-Label) also, netlabels should have some connection to wire. i expect the label to appear as an attribute of the specific wire its connected to. just my 2c

 If I may summarise, the essence of this feature request is: "the fact you **can** assign two netlabels to the same net is bad." The user should get a clear warning/sign that they are about to overwrite one netlabel with another. Leaving two netlabels on the same net without clear rules about which one takes precedence, doesn't make sense.

@andyfierman - yes, thank you for clarifying. hope to see this getting sorted. with your fast dev cycle i expect it will.

Hi Issue confirmed, we will fix this ASAP,  next week we will release a new version to solve this issue. That is because of the 3 decimals supporting impact. thank you.

hi This issue fixed in v5.4.12, please update to this version. thank you.