![andyfierman](https://easyeda.com/images/avatar-default.png)
DRC = Design Rules Check
posted by andyfierman ,
10 years ago.
replied by rdg_engsvcs ,
6 years ago.
![andyfierman](https://easyeda.com/images/avatar-default.png)
XY flip in PCB is dangerous!
posted by andyfierman ,
10 years ago.
replied by dillon ,
10 years ago.
![andyfierman](https://easyeda.com/images/avatar-default.png)
PCB refresh reverts to earlier saved view
posted by andyfierman ,
10 years ago.
replied by dillon ,
10 years ago.
![andyfierman](https://easyeda.com/images/avatar-default.png)
Trace time readout too many decimal places
posted by andyfierman ,
10 years ago.
replied by dillon ,
10 years ago.
![andyfierman](https://easyeda.com/images/avatar-default.png)
Traces vs. data grid rounding errors
posted by andyfierman ,
10 years ago.
replied by dillon ,
10 years ago.